Quantum modulation of the channel charge and distributed capacitance of double gated nanosize FETs

The structure represents symmetrical metal electrode (gate 1) – front SiO2 layer – n-Si nanowire FET – buried SiO2 layer – metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 – front SiO2 and gate 2 – buried SiO2 interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ~uF⁄cm2 . The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.